Parallel Computer Architecture (English)

   Wednesday, April 17, 2024   

Starting a new Lecture Notes Series on Parallel Computer Architecture

Youtube Lecture Playlist Credits 

Channel Name: NPTEL IIT Guwahati

So Let Us Start to This Journey of Learning 

Parallel Computer Architecture By Lecture Notes together!

Lecture 1: Parallel Computer Architecture

Lecture 2: Lec 1: Why do we need parallel architecture ?

Lecture 3: Lec 2: Multicore Revolution

Lecture 4: Lec 3: What is Parallel Architecture?

Lecture 5: Lec 4: Performance and Benchmarking

Lecture 6: Lec 5: Reporting Results

Lecture 7: Lec 6: Some Laws

Lecture 8: Lec 7: A shift from sequential to parallel

Lecture 9: Lec 8: Programming Models

Lecture 10: Lec 9: Shared Memory Paradigm

Lecture 11: Lec 10: Message Passing Paradigm

Lecture 12: Lec 11: Examples

Lecture 13: Lec 12: Cache Basics

Lecture 14: Lec 13: Memory hierarchy questions (1)

Lecture 15: Lec 14: Memory hierarchy questions (2)

Lecture 16: Lec 15: Six basic cache optimisations (1)

Lecture 17: Lec 16: Six basic cache optimisations (2)

Lecture 18: Lec 17: Virtual Memory (1)

Lecture 19: Lec 18: Virtual Memory (2)

Lecture 20: Lec 19: Cache Coherence Problem

Lecture 21: Lec 20: Concept of Serialisation

Lecture 22: Lec 21: Coherence related Conditions

Lecture 23: Lec 22: Types of Coherence Protocols (1)

Lecture 24: Lec 23: Types of Coherence Protocols (2)

Lecture 25: Lec 24: VI Protocol

Lecture 26: Lec 25: 3 state: MSI Protocol

Lecture 27: Lec 26: MESI Protocol

Lecture 28: Lec 27: Dragon Protocol

Lecture 29: Lec 28: Coherence misses

Lecture 30: Lec 29: Coherence misses example

Lecture 31: Lec 30: Correctness Requirements

Lecture 32: Lec 31: Single-Level caches with an Atomic Bus (1)

Lecture 33: Lec 32: Single-Level caches with an Atomic Bus (2)

Lecture 34: Lec 33: Multi-Level caches with an Atomic Bus (1)

Lecture 35: Lec 34: Multi-Level caches with an Atomic Bus (2)

Lecture 36: Lec 35: Split transaction Bus

Lecture 37: Lec 36: Phases in Split Transaction Bus

Lecture 38: Lec 37: Request table and Organization

Lecture 39: Lec 38: Path of a Cache Miss

Lecture 40: Lec 39: Multi-Level cache + Split transaction Bus

Lecture 41: Lec 40: Introduction to Directory Cache Coherence

Lecture 42: Lec 41: Basic Operation of a Directory

Lecture 43: Lec 43: Directory Overhead Optimisations

Lecture 44: Lec 44: Directory Protocol optimisations

Lecture 45: Lec 45:Proving Correctness (1)

Lecture 46: Lec 46: Proving Correctness (2)

Lecture 47: Lec 42: Directory Organisations

Lecture 48: Lec 47: SGI Origin Architecture

Lecture 49: Lec 48: Working of protocol

Lecture 50: Lec 49: Correctness Issues

Lecture 51: Lec 50: Sequent NUMA-Q Architecture

Lecture 52: Lec 51: Working of protocol(1)

Lecture 53: Lec 52: Working of protocol (2)

Lecture 54: Lec 53: Correctness and Protocol Interaction

Lecture 55: Lec 54: Sequential Consistency

Lecture 56: Lec 55: Implications of Sequential Consistency

Lecture 57: Lec 56: Relaxed Consistency Models (1)

Lecture 58: Lec 57: Relaxed Consistency Models (2)

Lecture 59: Lec 58: Relaxing all Orders

Lecture 60: Lec 59: Uninterruptible Instructions

Lecture 61: Lec 60: Implementation of atomic instructions

Lecture 62: Lec70: Other synchronisation options

Lecture 63: Lec 71: Interconnect Overview

Lecture 64: Lec 72: Topologies

Lecture 65: Lec 73: Routing

Lecture 66: Lec 74: Flow Control