Electronics - Digital System design with PLDs and FPGAs (English)

   Friday, April 25, 2025   

Starting a new Lecture Notes Series on Electronics - Digital System design with PLDs and FPGAs

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Electronics - Digital System design with PLDs and FPGAs By Lecture Notes together!

Lecture 1: Mod-01 Lec-01 Course Contents, Objective

Lecture 2: Mod-01 Lec-02 Revision of Prerequisite

Lecture 3: Mod-01 Lec-03 Design of Synchronous Sequential Circuits

Lecture 4: Mod-02 Lec-04 Analysis of Synchronous Sequential Circuits

Lecture 5: Mod-02 Lec-05 Top-down Design

Lecture 6: Mod-02 Lec-06 Controller Design

Lecture 7: Mod-02 Lec-07 Control algorithm and State diagram

Lecture 8: Mod-02 Lec-08 Case study 1

Lecture 9: Mod-03 Lec-09 Entity, Architecture and Operators

Lecture 10: Mod-03 Lec-10 Concurrency, Data flow and Behavioural models

Lecture 11: Mod-03 Lec-11 Structural Model, Simulation

Lecture 12: Mod-03 Lec-12 Simulating Concurrency

Lecture 13: Mod-03 Lec-13 Classes and Data types

Lecture 14: Mod-03 Lec-14 Concurrent statements and Sequential statements

Lecture 15: Mod-03 Lec-15 Sequential statements and Loops

Lecture 16: Mod-03 Lec-16 Modelling flip-flops, Registers

Lecture 17: Mod-03 Lec-17 Synthesis of Sequential circuits

Lecture 18: Mod-03 Lec-18 Libraries and Packages

Lecture 19: Mod-03 Lec-19 Operators, Delay modelling

Lecture 20: Mod-03 Lec-20 Delay modelling

Lecture 21: Mod-03 Lec-21 VHDL Examples

Lecture 22: Mod-04 Lec-22 VHDL Examples, FSM Clock

Lecture 23: Mod-02 Lec-23 FSM issues 1

Lecture 24: Mod-02 Lec-24 FSM Issues 2

Lecture 25: Mod-02 Lec-25 FSM Issues 3

Lecture 26: Mod-03 Lec-26 VHDL coding of FSM

Lecture 27: Mod-02 Lec-27 FSM Issues 4

Lecture 28: Mod-02 Lec-28 FSM Issues 5

Lecture 29: Mod-02 Lec-29 Synchronization 1

Lecture 30: Mod-02 Lec-30 Synchronization 2

Lecture 31: Mod-05 Lec-31 Evolution of PLDs

Lecture 32: Mod-02 Lec-32 Simple PLDs

Lecture 33: Mod-05 Lec-33 Simple PLDs: Fitting

Lecture 34: Mod-05 Lec-34 Complex PLDs

Lecture 35: Mod-06 Lec-35 FPGA Introduction

Lecture 36: Mod-06 Lec-36 FPGA Interconnection, Design Methodology

Lecture 37: Mod-06 Lec-37 Xilinx Virtex FPGA’s CLB

Lecture 38: Mod-06 Lec-38 Xilinx Virtex Resource Mapping, IO Block

Lecture 39: Mod-06 Lec-39 Xilinx Virtex Clock Tree

Lecture 40: Mod-06 Lec-40 FPGA Configuration

Lecture 41: Mod-06 Lec-41 Altera and Actel FPGAs

Lecture 42: Mod-03 Lec-42 VHDL Test bench

Lecture 43: Mod-02 Lec-43 Case study 2

Lecture 44: Mod-02 Lec-44 Case study on FPGA Board