Starting a new Lecture Notes Series on Embedded Systems - Design Verification and Test
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Embedded Systems - Design Verification and Test By Lecture Notes together!
Lecture 2: Introduction
Lecture 3: Modeling Techniques – 1
Lecture 4: Modeling Techniques – 2
Lecture 5: Hardware/Software Partitioning - 1
Lecture 6: Hardware/Software Partitioning - 2
Lecture 7: Introduction to Hardware Design
Lecture 8: Hardware Architectural Synthesis – 1
Lecture 9: Hardware Architectural Synthesis – 2
Lecture 10: Hardware Architectural Synthesis – 3
Lecture 11: Hardware Architectural Synthesis – 4
Lecture 12: Hardware Architectural Synthesis – 5
Lecture 13: Hardware Architectural Synthesis – 6
Lecture 14: Hardware Architectural Synthesis – 7
Lecture 15: System Level Analysis
Lecture 16: Uniprocessor Scheduling – 1
Lecture 17: Uniprocessor Scheduling – 2
Lecture 18: Multiprocessor Scheduling – 1
Lecture 19: Multiprocessor Scheduling – 2
Lecture 21: Syntax and Semantics of CTL
Lecture 22: Equivalence between CTL formulas
Lecture 23: Model Checking Algorithm
Lecture 24: Binary Decision Diagram
Lecture 25: Use of OBDDs for State Transition System
Lecture 26: Symbolic Model Checking
Lecture 27: Introduction to Digital VLSI Testing
Lecture 28: Automatic Test Pattern Generation (ATPG)
Lecture 29: Scan Chain based Sequential Circuit Testing
Lecture 30: Software-Hardware Co-validation Fault Models and High Level Testing for Complex Embedded Systems
Lecture 31: Testing for embedded cores
Lecture 32: Bus and Memory Testing
Lecture 34: BIST for Embedded Systems
Lecture 37: Testing for Reprogrammable hardware