Digital Design with Verilog (English)

   Wednesday, April 17, 2024   

Starting a new Lecture Notes Series on Digital Design with Verilog

Youtube Lecture Playlist Credits 

Channel Name: NPTEL IIT Guwahati

So Let Us Start to This Journey of Learning 

Digital Design with Verilog By Lecture Notes together!

Lecture 1: Digital Design with Verilog

Lecture 2: Lec 1: Introduction to Digital Design with Verilog

Lecture 3: Lec 2: Switching Algebra

Lecture 4: Lec 3: Canonical Forms of Switching Functions

Lecture 5: Lec 4: Number Systems

Lecture 6: Lec 5: Binary Arithmetic

Lecture 7: Lec 6: Binary Codes

Lecture 8: Lec 7: Error Detection and Corrections Codes

Lecture 9: Lec 8: Minimization of Switching functions-Karnaugh Map

Lecture 10: Lec 9: Karnaugh Map

Lecture 11: Lec 10: Minimization of Switching functions-Properties

Lecture 12: Lec 11: Quine-McCluskey Method

Lecture 13: Lec 12: Quine-McCluskey Method-Prime Implication Chart

Lecture 14: Lec 13: ESPRESSO-Heuristic Based Switching Function Minimization

Lecture 15: Lec 14: Multi-level Logic Minimization

Lecture 16: Lec 15: Multi-level Logic Minimization-Kernels Extraction

Lecture 17: Lec 16: Digital Circuits Modelling using Verilog

Lecture 18: Lec 17: Modelling Techniques in Verilog

Lecture 19: Lec 18: Behavioral Modelling in Verilog

Lecture 20: Lec 19: Digital System Design using Verilog

Lecture 21: Lec 20: Testbench in Verilog

Lecture 22: Lec 21: Code Conversion, Parity Bit Generator

Lecture 23: Lec 22: Comparator, Multiplexer

Lecture 24: Lec 23: Encoder, Decoder

Lecture 25: Lec 24: Ripple Carry Adder, Carry Look ahead Adder

Lecture 26: Lec 25: Adder/Subtractor

Lecture 27: Lec 26: BCD Adder, Multiplier

Lecture 28: Lec 27:Latch/Storage Design

Lecture 29: Lec 28:Flipflop Design, Characteristics of Flipflop

Lecture 30: Lec 29:Flipflop, Register and Memory

Lecture 31: Lec 30: Digital Counter

Lecture 32: Lec 31: Finite State Machine Design and Implementation with many Examples

Lecture 33: Lec 32: FSM Completeness and Correctness

Lecture 34: Lec 33: Sync Counter using FSM, Implementation using different FFs and Comparision of types of FSM

Lecture 35: Lec 34: FSM State Optimization using Row Matching and Partitioning Methods

Lecture 36: Lec 35: State Optimization using Implication chart and State Encoding

Lecture 37: Lec 36: RTL Design, Introduction to ASM (Algorithmic State Machine)

Lecture 38: Lec 37:RTL/ASM Design Examples and Implementation

Lecture 39: Lec 38: ASM Data Path Inference and Control Path Generation

Lecture 40: Lec 39: Sequential Multplier the Classic Example of RTL Design

Lecture 41: Lec 40: Introduction to FPGA and Design Flow

Lecture 42: Lec 41: Introduction to Electronic Design Automation