Computer-Design Verification & Test of Digital VLSI Circuits (English)

   Friday, March 28, 2025   

Starting a new Lecture Notes Series on Computer-Design Verification & Test of Digital VLSI Circuits

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Computer-Design Verification & Test of Digital VLSI Circuits By Lecture Notes together!

Lecture 1: Mod-01 Lec-01 Introduction to Digital VLSI Design Flow

Lecture 2: Mod-01 Lec-02 High Level Design Representation

Lecture 3: Mod-01 Lec-03 Transformations for High Level Synthesis

Lecture 4: Mod-02 Lec-01 Introduction to HLS: Scheduling, Allocation and Binding Problem

Lecture 5: Mod-02 Lec-02 Scheduling Algorithms-1

Lecture 6: Mod-02 Lec-03 Scheduling Algorithms-2

Lecture 7: Mod-02 Lec-04 Binding and Allocation Algorithms

Lecture 8: Mod-03 Lec-01 Two level Boolean Logic Synthesis-1

Lecture 9: Mod-03 Lec-02 Two level Boolean Logic Synthesis-2

Lecture 10: Mod-03 Lec-03 Two level Boolean Logic Synthesis-3

Lecture 11: Mod-03 Lec-04 Heuristic Minimization of Two-Level Circuits

Lecture 12: Mod-03 Lec-05 Finite State Machine Synthesis

Lecture 13: Mod-03 Lec-06 Multilevel Implementation

Lecture 14: Mod-04 Lec-01 Introduction to formal methods for design verification

Lecture 15: Mod-04 Lec-02 Temporal Logic: Introduction and Basic Operators

Lecture 16: Mod-04 Lec-03 Syntax and Semantics of CTL

Lecture 17: Mod-04 Lec-04 Syntax and Semantics of CTL -- Continued

Lecture 18: Mod-04 Lec-05 Equivalence between CTL Formulas

Lecture 19: Mod-05 Lec-01 Introduction to Model Checking

Lecture 20: Mod-05 Lec-02 Model Checking Algorithms I

Lecture 21: Mod-05 Lec-03 Model Checking Algorithms II

Lecture 22: Mod-05 Lec-04 Model Checking with Fairness

Lecture 23: Mod-06 Lec-01 Binary Decision Diagram: Introduction and construction

Lecture 24: Mod-06 Lec-02 Ordered Binary Decision Diagram

Lecture 25: Mod-06 Lec-03 Operation on Ordered Binary Decision Diagram

Lecture 26: Mod-06 Lec-04 Ordered Binary Decision Diagram for State Transition Systems

Lecture 27: Mod-06 Lec-05 Symbolic Model Checking

Lecture 28: Mod-07 Lec-01 Introduction to Digital VLSI Testing

Lecture 29: Mod-07 Lec-02 Functional and Structural Testing

Lecture 30: Mod-07 Lec-03 Fault Equivalence

Lecture 31: Mod-08 Lec-01 Fault Simulation-1

Lecture 32: Mod-08 Lec-02 Fault Simulation-2

Lecture 33: Mod-08 Lec-03 Fault Simulation-3

Lecture 34: Mod-08 Lec-04 Testability Measures (SCOAP)

Lecture 35: Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras

Lecture 36: Mod-09 Lec-02 D-Algorithm-1

Lecture 37: Mod-09 Lec-03 D-Algorithm-2

Lecture 38: Mod-10 Lec-01 ATPG for Synchronous Sequential Circuits

Lecture 39: Mod-10 Lec-02 Scan Chain based Sequential Circuit Testing-1

Lecture 40: Mod-10 Lec-03 Scan Chain based Sequential Circuit Testing-2

Lecture 41: Mod-11 Lec-01 Built in Self Test-1

Lecture 42: MMod-11 Lec-02 Built in Self Test-2

Lecture 43: Mod-11 Lec-03 Memory Testing-1

Lecture 44: Mod-11 Lec-04 Memory Testing-2