System Design Through VERILOG (English)

   Thursday, April 04, 2024   

Starting a new Lecture Notes Series on System Design Through VERILOG

Youtube Lecture Playlist Credits 

Channel Name: NPTEL IIT Guwahati

So Let Us Start to This Journey of Learning 

System Design Through VERILOG By Lecture Notes together!

Lecture 1: System Design Through VERILOG

Lecture 2: Lec 1: Verilog Operators and Modules

Lecture 3: Lec 2: Verilog Ports, Data types and Assignments

Lecture 4: Lec 3: Basics of gate level modeling

Lecture 5: Lec 4: Half adder, full adder and ripple carry adde

Lecture 6: Lec 5: Parallel adder/subtractor

Lecture 7: Lec 6: Multiplier and comparator

Lecture 8: Lec 7: Decoder, encoder and multiplexer

Lecture 9: Lec 8: Demultiplexer, read only memory

Lecture 10: Lec 9: Review of flip-flops

Lecture 11: Lec 10: Verilog modeling of flip-flops

Lecture 12: Lec 11: Modeling of CMOS gates and Boolean functions

Lecture 13: Lec 12: Modeling using transmission gates, CMOS dalay times

Lecture 14: Lec 13: Signal strengths

Lecture 15: Lec 14: Basics of dataflow modeling

Lecture 16: Lec 15: Examples of dataflow modeling

Lecture 17: Lec 16: Basics of behavioral modeling

Lecture 18: Lec 17: Examples of behavioral modeling

Lecture 19: Lec 18: Verilog modeling of counters

Lecture 20: Lec 19: Verilog modeling of sequence detector

Lecture 21: Lec 20: Verilog modeling FSMs and shift registers

Lecture 22: Lec 21: Combinational circuit examples

Lecture 23: Lec 22: Sequential circuit examples

Lecture 24: Lec 23: Arithmetic and Logic Unit (ALU)

Lecture 25: Lec 24: Static RAM and Braun Multiplier

Lecture 26: Lec 25: FIR filter implementation

Lecture 27: Lec 26: Baugh-Wooley signed multiplier architecture

Lecture 28: Lec 27: IIR filter implementation